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GD25D10b datasheet http://www.elm-tech.com
- content - page 1 . f eatures --------------------------- --------------------------- ---------------------------- - -------------- 4 2. general description ------------------------------------------------------ - ---------------------- 5 3. memory organization --------------------------------------------------------- - ---------------- 6 4. device operation ----------------------------------------------------------------- - - - - - - - - - ------ -- 6 5. data protection ----------------------------------------------------------------------- - - - - - ------- - 6 6. status register -------------------------------------------------------------- - - - - - - - - - - - - - - - -------- 7 7. commands description ------------------------------------------- --- - - - - - - - - - - - - - - - - - --------- - 8 table of id definition ------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - ------------ - 9 7.1. write enable (wren) (06h) ------------------------------------------------------- - - - - - - - - - - - - ------- 10 7.2. write disable (wrdi) (04h) -------------------------------------------------------------- - - - - - - - - - - 10 7.3. r ead status register (wdsr) (05h) ---------- ------------------------ -------------- ------- ----- - - -- 10 7.4. write status register (wrsr) (01h) ------------------------------------------------------- - ------- 11 7.5. read data bytes (read) (03h) ---------- ------------------------ -------------- ------- -- - - - - - - - ----- 1 2 7.6 . read data bytes at higher speed (fast read) (0bh) ---------------------------------------------- 1 2 7.7. dual output fast read (3bh) ----------------------------------------------------- - - - - - - - - - - - - - ------- 13 7.8. page program (pp) (02h) ------------------------------------------------------- - - - - - - - - - - - - - - ------- 13 7.9. fast page program ( fpp ) (f2h) --------------------------------------------------------- - - - - - ------ 1 4 7.10. sector erase (se) (20h) ----------------------------------------------------------------------------- 1 5 7.11. 32kb block erase (be) (52h) --------------------------------------------------------------------- 1 6 7.12. 64 kb block erase (be) (d8h) ------------------------------------------------------ - - - - - - - - - ------ 1 6 7.13. chip erase (ce) (60/c7h) -------------------------------------------------------------------------- 17 7. 14 . deep power-down (dp) (b9h) ---------------------------------------------------------------- - --- - 1 7 7.15. release from deep power-down / read device id (abh) --------------------------------------- 1 8 7.16. read manufacture id / device id (rems) (90h) ---------- -------- -------------- - --- ----- ------- 19 7.17. read identification (rdid) (9fh) ---------------------------------------------------------- ------- 2 0 8 . electrical characteristics ------------------------------------------- - ------------------- 2 1 8 .1. power- on timing ------------------------------------------------------------------------------------- 21 8 .2. initial delivery state ---------------------------------------------------------------------------------- 2 1 8 .3. data retention and endurance ----------------------------------------------------------------------- 21 8 .4. latch up characteristics ----------------------------------------------------------------------------- 2 1 8 .5. abso lute maximum ratings ------------------------------------------------------------------------- 2 2 8 .6 . capacitance measurement co nditions -------------------------------------------------------- - ---- 2 2 8 .7. dc characteristics ----------------------------------------------------------------------------------- 2 3 8 .8. a c characteristics --------------------------------------------------------------------------- -------- 2 4 GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com
9 . ordering information --------------------------------------------------- --------------------- - 2 6 10 . package information ------------------------------------------- ------------------------------- - 2 7 10 .1. package sop8 150mil ------------------------------------------------ ---------------------------- 27 10.2. package uson8 (3x2mm) ----------------------------------------------------------------------- 2 8 GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com
4 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 1. features ? 1m-bit serial flash - 128k/64k-byte - 256 bytes per programmable page ? standard, dual output - standard spi: sclk, cs#, si, so, wp# - dual output: sclk, cs#, io0, o1, wp# ? clock frequency - 80mhz for fast read with 30pf load - dual output da ta transfer up to 160mbits/s ? software/hardware write protection - w rite protect all/portion of memory via software - enable/disable protection with wp# pin ? cycling endurance - minimum 100,000 program/erase cycles ? data retention - 20-year data retention typical ? program/erase speed - page program time: 0.7ms typical - sector erase time: 40ms typical - block e rase time: 0.2/0.4s typical - chip e rase time: 0.8/0.4s typical ? flexible architecture - sector of 4k-byte - block of 32/64k-byte ? low power consumption - 18ma maximum active current - 5a maximum power down current ? single power supply voltage - full voltage range: 2.7~3.6v ? package option - sop8 150mil - u son8 3x2mm
5 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com s p i c o m m a n d & c o n t r o l l o g i c h i g h v o l t a g e g e n e r a t o r s p a g e a d d r e s s l a t c h / c o u n t e r s t a t u s r e g i s t e r w r i t e c o n t r o l l o g i c b y t e a d d r e s s l a t c h / c o u n t e r c o l u m n d e c o d e a n d 2 5 6 - b y t e p a g e b u f f e r w r i t e p r o t e c t l o g i c a n d r o w d e c o d e f l a s h m e m o r y c s # s c l k s i ( i o 0 ) s o ( o 1 ) w p # pin name i / o description cs# i chip select input so (o1) o data output ( data output 1 ) wp# i write protect input vss ground si (io0) i / o data input ( data input output 0 ) sclk i serial clock input nc no connection vcc power supply pin description 2. general description the GD25D10b (1m-bit) serial flash supports the standard serial peripheral interface (spi), and supports the dual output: serial clock, chip select, serial data i/o0 (si), o1 (so). the dual output data is transferred with speed of 160mbits/s. connection diagram 8-lead sop 8-lead uso n block diagram
6 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com each device has each block has each sector has each page has 128 k 64/32k 4k 256 bytes 512 256/128 16 - pages 32 16/8 - - sectors 2/4 - - - blocks 3. memory organization uniform block sector architecture block sector address range 1 31 01f000h 01ffffh ----- ----- ----- 16 010000h 010fffh 0 15 00f000h 00ffffh ----- ----- ----- 0 000000h 000fffh 4 . device operation spi mode standard spi the GD25D10b features a serial peripheral interface on 4 si gnals bus: serial clock (sclk), chip select (cs#), s erial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk. dual spi the GD25D10b supports dual output operation when using the dual output fast read (3bh) commands. these commands allow data to be transferred to or from the device at two times the rate of the standard spi. when using the dual output command the si and so pins become bidirectional i/o pins: io0 and o1. 5 . data protection the GD25D10b provides the following data protection methods: ? write enable (wren) command: the wren command is set the write enable latch bit (wel). the wel bit will reset to 0 in the following situations: - power-up - write disable (wrdi) - write status register (wrsr) - page program (pp) - sector erase (se) / block erase (be) / chip erase (ce)
7 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com ? software protection mode: the block protect (bp2, bp1, bp0) bits define the section of the protected memory area which is read-only and unalterable. ? hardware protection mode: wp# going low to protected the bp0~bp2 bits and srp bits. ? deep power-down mode: in deep power-down mode, all commands are ignored except the release from deep power-down mode command. ? write inhibit voltage (vwi): device would reset automatically when vcc is below a certain threshold vwi. status register content memory content bp2 bp1 bp0 blocks addresses density portion 0 0 0 none none none none 0 0 1 sector 0 to 29 00 0000h-01dfffh 120 kb lower 30/32 0 1 0 sector 0 to 2 7 00 0000h-01bfffh 112 kb lower 28/ 32 0 1 1 sector 0 to 2 3 00 0000h-017fffh 96kb lower 24/ 32 1 0 0 sector 0 to 15 0 00000h-00ffffh 64k b lower 16/ 32 1 0 1 all 0 00000h-01ffffh 128kb all 1 1 all 0 00000h-01ffffh 128 k b all table 1. GD25D10b protected area size 6 . status register the status and control bits of the status register are as fo llows: w ip bit. the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit is set to 1, it means th e device is busy in program/erase/write status register progress. when wip bit is cleared to 0 , it means the device is no t in program/erase/write status register progress. the default va lue of wip is 0 . wel bit. the write enable lat ch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable lat ch is set, when set to 0 the internal write enable lat ch is reset and no write sta tus register , program or erase command is accepted. the default value of wel is 0. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase commands. these bits are writ ten with the w rite statue register (wrsr) command. when the block protect (bp2, bp1, bp0) bits are set to 1, the relevant memory area (as de fined in table1). becomes protected against page program (pp) , sector erase (se) and block erase (be) commands. s7 s6 s5 s4 s3 s2 s1 s0 srp reserved reserved bp2 bp1 bp0 wel wip
8 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com the block protect (bp2, bp1, bp0) bits can be writ ten provided that the hardware protected mode has not been set. the chip erase (ce) command is executed,if the block protect (bp2, bp1, bp0) bits are all 0.the default value of bp2:0 are 0s. sr p bit. the status register protect (srp) bit operates in conjunction with the write protect (wp#) signal. the status register write protect (srp) bit and write protect (wp#) signal set the device to the hardware protected mode. when the status register protect (srp) bit is set to 1, and write protect (wp#) is driven low. in this mode, the non-volatile bits of the status register (srp, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is not execution. the default value of srp is 0. srp #wp status register description 0 software protected the status register can be written to after a write enable command, wel=1.(default) 1 0 hardware protected wp#=0, the status register locked and can not be written to. 1 1 hardware unprotected wp#=1, the status register is unlocked and can be written to after a write enable command, wel=1. 7. commands description all commands, addresses and data are shifted in and out of the device by the host system, with the most significant bit first. on the first rising edge of sclk after cs# is driven low, the one-byte command code must be shifted into the device, with the most significant bit first on si, each bit being latched on the rising edges of sclk. see table2, every command sequence starts with a one-byte command code. depending on the command, this might be followed by address bytes, or data bytes, or dummy bytes. cs# must be driven high after the last bit of the command sequence has been shifted in. for the command of read, fast read, read status register or release from deep power-down, and read device id, the shifted-in command sequence is followed by a data-out sequence. cs# can be driven high after any bit of the data-out sequence is being shifted out. for the command of page program, sector erase, block erase, chip erase, write status register, write enable, write disable or deep power-down command, cs# must be driven high exactly at a byte boundary, which means the clock pulse number should be an exact multiple of eight. otherwise the command is rejected to executed. especially for page program command, i f at any time the input end is not a completed byte, nothing will be written into the memory array, neither would wel bit be reset.
9 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7-s0) (continuous) write status register 01h (s7-s0) read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) (continuous) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (continuous) dual output fast read 3bh a23-a16 a15-a8 a7-a0 dummy d7-d0 (1) (continuous) page program 02h a23-a16 a15-a8 a7-a0 (d7-d0) next byte fast page program f2h a23-a16 a15-a8 a7-a0 (d7-d0) next byte sector erase 20h a23-a16 a15-a8 a7-a0 block erase (32k) 52h a23-a16 a15-a8 a7-a0 block erase (64k) d8h a23-a16 a15-a8 a7-a0 chip erase c7/60h deep power-down b9h r elease from deep power-down, and read device id abh dummy dummy dummy (did7- did0) (continuous) r elease from deep power-down abh m anufacturer/device id 90h dummy dummy 00h (mid7- mid0) (did7- did0) (continuous) read identification 9fh (mid7-mid0) (jdid15-jdid8) (jdid7-jdid0) (continuous) table 2. commands note: (1) dual output data io0 = (d6, d4, d2, d0) o1 = (d7, d5, d3, d1) table of id definitions : operation code m7-m0 id15-id8 id7-id0 9fh c8 40 11 90h c8 10 abh 10
10 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 7.1 . write enable (wren)(06h) the write enable (wren) command is for setting the write enable latch (wel) bit to 1. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), block erase (be), chip erase (ce) and write status register (wrsr) command. the write enable (wren) command sequence: cs# goes low sending the write enable command cs# goes high. figure 1. write enable sequence diagram command 0 1 2 3 4 5 6 7 06 h cs # sclk si so high - z 7.2. write disable (wrdi) (04h) the write disable command is for resetting the write enable latch (wel) bit to 0. the wel bit is reset by following condition: power-up and upon completion of the write status register, page program, sector erase, block erase and chip erase commands. the write disable command sequence: cs# goes low sending the write disable command cs# goes high. figure 2. write disable sequence diagram command 0 1 2 3 4 5 6 7 04 h cs # sclk si so high - z 7.3 . read status register (rdsr) (05h) the read status register (rdsr) command is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new command to the device. it is also possible to read the status register continuously. for command code 05h, the so will output status register bits s7~s0.
11 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 3. read status register sequence diagram command 0 1 2 3 4 5 6 7 05 h cs # sclk si so high - z 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 msb s 7 ~ s 0 out s 7 ~ s 0 out msb 7.4. write status register (wrsr) (01h) the write status register (wrsr) instruction allows new values to be written to the status register. a write enable (wren) instruction must be executed previously to set the write enable latch (wel) bit, before it can be accepted. the write status register (wrsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data byte on serial data input (di). the write status register (wrsr) instruction has no effe ct on s6, s5, s1 and s0 of the status register. s6 and s5 are always read as 0. chip select (cs#) m ust be dri ven h i gh after the eighth bit of the data byte has been latched in. otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select (cs#) is dri ven h i gh, the self-timed write status register cycle (the duration is tw) is initiated. while the write status register cycle is in progress, reading status register to check the write in progress (wip) bit is achievable. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and turn to 0 on the completion of the write status register . when the cycle is completed, the write enable latch (wel) is reset to 0. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, which are utilized to define the size of the read-only area. the write status register (wrsr) instruction also allows the user to set or reset the status register protect (srp) bit in accordance with the write protect (wp#) signal, by setting which t he device can enter into hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once enter into the hardware protected mode (hpm). figure 4. write status register sequence diagram c o m m a n d 0 1 2 3 4 5 6 7 0 1 h c s # s c l k s i s o h i g h - z 8 9 1 0 1 1 1 2 1 3 1 4 1 5 m s b 7 6 5 4 3 2 1 0 s t a t u s r e g i s t e r i n
12 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 7.5 . read data bytes (read) (03h) the read data bytes (read) command is followed by a 3-byte address (a23-a0), each bit being latched- in on the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f r , on the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) command. any read data bytes (read) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 5. read data bytes sequence diagram 7.6 . read data bytes at higher speed (fast read) (0bh) the read data bytes at higher speed (fast read) command is for quickly reading data out. it is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in on the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f c , on the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 6. read data bytes at higher speed sequence diagram
13 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 7.7 . dual output fast read (3bh) the dual output fast read command is followed by 3-byte address (a23-a0) and a dummy byte, each bit being latched in on the rising edge of sclk, then the memory contents are shifted out 2-bit per clock cycle from si and so. the command sequence is shown in followed figure7. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 7. dual output fast read sequence diagram 7.8 . page program (pp) (02h) the page program (pp) command is for programming the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the page program (pp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page program command 3-byte address on si at least 1 byte data on si cs# goes high. the command sequence is shown in figure8. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the page program (pp) command is not executed. as soon as cs# is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset.
14 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 8. page program sequence diagram a page program (pp) command is not executed when it is applied to a page protected by the block protect (bp2, bp1, bp0). 7.9 . fast page program (fpp) (f2h) the fast page program (fpp) command is for programming the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the fast page program (fpp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page program command 3-byte address on si at least 1 byte data on si cs# goes high. the command sequence is shown in figure9. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the fast page program (fpp) command is not executed. as soon as cs# is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a fast page program (fpp) command is not executed when it is applied to a page protected by the block protect (bp2, bp1, bp0).
15 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 9. fast page program sequence diagram figure 10. sector erase sequence diagram command 0 1 2 3 4 5 6 7 20 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7.10 . sector erase (se) (20h) the sector erase (se) command is for erasing the all data of the specific sector. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the sector erase (se) command is entered by driving cs# low, followed by the command code, and 3-address byte on si. any address inside the sector is a valid address for the sector erase (se) command. cs# must be driven low for the entire duration of the sequence. the sector erase command sequence: cs# goes low sending sector erase command 3-byte address on si cs# goes high. the command sequence is shown in figure10. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the sector erase (se) command is not executed. as soon as cs# is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register is accessed to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and becomes 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) command applied to a sector which is protected by the block protect (bp2, bp1, bp0) bit (see table1) is not executed.
16 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 7. 11 . 32kb block erase (be) (52h) the 32kb block erase (be) command is for erasing the all data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 32kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 32kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 32kb block erase command sequence: cs# goes low sending 32kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure11. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register is accessed to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and becomes 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 32kb block erase (be) command applied to a block which is protected by the block protect (bp2, bp1, bp0) bits (see table1) is not executed. figure 11. 32kb block erase sequence diagram command 0 1 2 3 4 5 6 7 52 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7.12 . 64kb block erase (be) (d8h) the 64kb block erase (be) command is for erasing the all data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 64kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 64kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 64kb block erase command sequence: cs# goes low sending 64kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure12. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register is accessed to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and becomes 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 64kb block erase (be) command applied to a block which is protected by the block protect (bp2, bp1, bp0) bits (see table1) is not executed.
17 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 12. 64kb block erase sequence diagram command 0 1 2 3 4 5 6 7 d8h cs # sc lk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7.1 3 . chip erase (ce) (60/c7h) the chip erase (ce) command is for erasing the all data of the chip. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit .the chip erase (ce) command is entered by driving cs# low, followed by the command code on serial data input (si). cs# must be driven low for the entire duration of the sequence. the chip erase command sequence: cs# goes low sending chip erase command cs# goes high. the command sequence is shown in figure13. cs# must be driven high after the eighth bit of the command code has been latched in, otherwise the chip erase command is not executed. as soon as cs# is driven high, the self- timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) command is executed if the block protect (bp2, bp1, bp0) bits are all 0 or all 1. the chip erase (ce) command is not executed if any sector is under protection. command 0 1 2 3 4 5 6 7 60h or c7h cs# sc lk si figure 13. chip erase sequence diagram 7.14 . deep power-down (dp) (b9h) executing the deep power-down (dp) command is the only way to enter the lowest consumption mode (the deep power-down mode). unlike deselecting the device by d riving cs# high, or entering into the standby mode (if there is no internal cycle currently in progress), the deep power-down mode provides an extra software protection mechanism while the device is not in active use. the only access to this mode is by executing the deep power-down (dp) command. since in the deep power-down mode, the device ignores all write, program and erase commands. once the device is in the deep power-down mode, all commands are ignored except the release from deep power-down and read device id (rdi) command. this releases the device from this mode. the release from deep power-down and read device id (rdi) command also allows the device id of the device to be output on so. the deep power-down mode automatically stops at power-down, and the device always power-up in the standby mode. the deep power-down (dp) command is entered by driving cs# low, followed by the command code on si. cs# must be driven low for the entire duration of the sequence.
18 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 14. deep power-down sequence diagram command 0 1 2 3 4 5 6 7 b9 h c s # s c lk si t dp stand-by mode deep power-down mode 7.15 . release from deep power-down / read device id (abh) the release from power-down and read device id command is a multi-purpose command, which can be used to release the device from the power-down state or obtain the devices electronic identification (id) number. when used to release the device from the power-down state, the command is issued by driving the cs# pin low, shifting the instruction code abh and driving cs# high as shown in figure15. release from power- down will take the time duration of t res1 (see ac characteristics) before the device will resume normal operation and other command are accepted. the cs# pin must keep high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the command is initiated by driving the cs# pin low and shifting the instruction code abh followed by 3-dummy byte. the device id bits are then shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure15. the device id value for the GD25D10b is listed in manufacturer and device identification table. the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the power-down state and obtain the device id, the command is the same as previously described, and shown in figure16, except that after cs# is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other command will be accepted. if the release from power-down and read device id command is issued while an erase, program or write cycle is in process (when wip equal 1) the command is ignored and will not have any effects on the current cycle. figure 15. release power-down sequence diagram command 0 1 2 3 4 5 6 7 abh cs # sclk si res 1 stand - by mode deep power - down mode t the deep power-down command sequence: cs# goes low sending deep power-down command cs# goes high. the command sequence is shown in figure14. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the deep power-down (dp) command is not executed. as soon as cs# is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power- down mode is entered. any deep power-down (dp) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
19 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 16. release power-down and read device id sequence diagram 7.16 . read manufacture id/device id (rems) (90h) the read manufacturer/device id command is an alternative to the release from power-down/device id command that provides both the jedec assigned manufacturer id and the specific device id. the command is initiated by driving the cs# pin low and shifting the command code 90h followed by a 24-bit address (a23-a0) of 000000h. after that, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure17. if the 24-bit address is initially set to 000001h, the device id will be read first. figure 17. read manufacture id/device id sequence diagram
20 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 7.17 . read identification (rdid) (9fh) the read identification (rdid) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. any read identification (rdid) command while an erase or program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) command should not be issued while the device is in deep power-down mode. the device is first selected by driving cs# to low. then, the 8-bit command code for the command is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the command sequence is shown in figure18. the read identification (rdid) command is terminated by driving cs# to high at any time during data output. when cs# is driven high, the device is put in the standby mode. once in the standby mode, the device waits to be selected, so that it can receive, decode and execute commands. figure 18. read identification id sequence diagram
21 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 8.1 . power-on timing symbol parameter min max unit tvsl vcc(min) to cs# low 10 us tpuw time delay from vcc(min) to write instruction 1 10 ms vwi write inhibit voltage vcc(min) 1 2.5 v table 3. power-up timing and write inhibit threshold 8. electrical characteristics 8 . 2 . initial delivery state the device is delivered with the memory array erased: all bits are set to 1(each byte contains ffh). the status register contains 00h (all status register bits are 0). 8 . 3 . data retention and endurance parameter test condition min unit minimum pattern data retention time 150c 10 years 125c 2 0 years erase / program endurance -40 to 85c 100k cycles 8 . 4 . latch up characteristics parameter min max input voltage respect to vss on i/o pins -1.0v vcc+1.0v vcc current -100ma 100ma
22 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 8 . 5 . absolute maximum ratings parameter value unit ambient operating temperature -40 to 85 c storage temperature -65 to 150 c output short circuit current 200 ma applied input/output voltage -0.5 to 4.0 v v cc -0.5 to 4.0 v 0.8v cc 0.1v cc 0.7v cc 0.2v cc 0.5v cc ac measurement level i nput timing reference level output timing re f erence level note : input pulse rise and fall time are <5ns 8 . 6 . capacitance measurement conditions symbol parameter min typ max unit conditions cin input capacitance 6 pf vin=0v cout output capacitance 8 pf vout=0v c l load capacitance 30 pf input rise and fall time 5 ns input pulse voltage 0.1vcc to 0.8vcc v input timing reference voltage 0.2vcc to 0.7vcc v output timing reference voltage 0.5vcc v figure 19. input test wave form and measurement level maximum negative overshoot waveform maximum positive overshoot waveform vss 20ns 20ns 20ns vss-2.0v vc c 20ns 20ns 20ns vcc + 2.0v
23 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 8. 7 . dc characteristics symbol parameter test condition min. typ. max. unit. i li input leakage current 2 a i l o output leakage current 2 a i cc1 standby current cs#=vcc, v in =vcc or vss 1 5 a i cc 2 deep power-down current cs#=vcc, v in =vcc or vss 1 5 a i cc 3 operating current (read) clk=0.1vcc/0.9vcc at 80mhz, q=open(*1 i/o, *2 output) 13 18 ma i cc 4 operating current (pp) cs#=vcc 10 ma i cc 5 operating current (wrsr) cs#=vcc 10 ma i cc 6 operating current (se) cs#=vcc 10 ma i cc 7 operating current (be) cs#=vcc 10 ma v il input low voltage -0.5 0.2vcc v v i h input high voltage 0.7vcc vcc+0.4 v v ol output low voltage l ol =1.6ma 0.4 v v o h output high voltage l oh =-100 a vcc-0.2 v (t= -40 c ~85 c , vcc=2.7~3.6v )
24 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 8. 8 . ac characteristics symbol parameter min. typ. max. unit. f c serial clock frequency for: dual output(3bh) dc. 80 mhz f r serial clock frequency for: read(03h) dc. 80 mhz t clh serial clock high time 4 ns t c ll serial clock low time 4 ns t clc h serial clock rise time (slew rate) 0.2 v/ns t chc l serial clock fall time (slew rate) 0.2 v/ns t slc h cs# active setup time 5 ns t chsh cs# active hold time 5 ns t s h ch cs# not active setup time 5 ns t c h sl cs# not active hold time 5 ns t shsl cs# high time (read/write) 20 ns t sh qz output disable time 6 ns t cl q x output hold time 0 ns t dvch data in setup time 2 ns t chdx data in hold time 2 ns t clq v clock low to output valid 6 ns t whsl write protect setup time before cs# low 20 ns t s hwl write protect hold time after cs# high 100 ns t dp cs# high to deep power-down mode 0.1 s t res1 cs# high to standby mode without electronic signature read 0.1 s t res 2 cs# high to standby mode with electronic signature read 0.1 s t w write status register cycle time 2 15 ms t pp page programming time 0.7 4.0 ms t f pp fast page programming time 0.5 4.0 ms t se sector erase time 4 0 200 ms t be1 block erase time(32k bytes) 0.2 0.6 s t b e2 block erase time(64k bytes) 0.4 1.0 s t ce chip erase time(GD25D10b) 0.8 2.0 s (t= -40 c ~85 c , vcc=2.7~3.6v, c l =30pf)
25 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com figure 20. serial input timing figure 21. output timing
26 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 9 . ordering information packing type y: tray r: tape & reel green code g: pb free & haloge n free green package temperature range i: industrial(-40 c to +85 c) package type t : sop8 150mil u: uson8 (32mm) generation b : version density 10 : 1mb series d : 3 v, 4kb uniform sector product family 25 : spi interface flash gd 25 d 1 0 b x i g x
27 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 10.1 package sop8 150mil 10 . package information detail " " gauge plane 1 4 5 8 e 1 e d a a 2 a 1 e b l l 1 c seating plane 0 . 10 symbol a a1 a2 b c d e e1 e l l1 ? unit mm min - 0.05 1.35 0.31 0.15 4.77 5.80 3.80 - 0.40 0.85 0 6 11 nom - - - - - 4.90 6.00 3.90 1.27 - 1.06 - 7 12 max 1.75 0.25 1.55 0.51 0.25 5.03 6.20 4.00 - 0.90 1.27 8 8 13 inch min - 0.002 0.053 0.012 0.006 0.188 - 0.149 - 0.016 0.033 0 6 11 nom - - - 0.016 - 0.193 0.236 0.154 0.050 0 0.042 - 7 12 max 0.069 0.010 0.061 0.020 0.010 0.198 - 0.158 - 0.035 0.050 8 8 13 dimensions note: both package length and width do not include mold flash.
28 r ev.1. 0 2 8 - GD25D10bxigx uniform sector dual and quad serial flash http://www.elm-tech.com 10.2 package uson8 (3 x2mm) 10.2. package uson8 ( 3*2mm ) dimensions symbol a a1 a2 b d d1 e e1 e y l unit mm min 0.50 0.13 0.18 2.90 0.15 1.90 1.50 0.00 0.30 nom 0.55 0.15 0.25 3.00 0.20 2.00 1.60 0.50 0.35 max 0.60 0.05 0.18 0.30 3.10 0.30 2.10 1.70 0.05 0.45 inch min 0.020 0.005 0.007 0.114 0.006 0.075 0.059 0.000 0.012 nom 0.022 0.006 0.010 0.118 0.008 0.079 0.063 0.020 0.014 max 0.024 0.002 0.007 0.012 0.122 0.012 0.083 0.067 0.002 0.018 note:both package length and width do not include mold flash. d e top view d1 e1 b e bottom view l 1 a2 a1 a side view y symbol a a1 a2 b d d1 e e1 e y l unit mm min 0.50 - 0.13 0.18 2.90 0.15 1.90 1.50 - 0.00 0.30 nom 0.55 - 0.15 0.25 3.00 0.20 2.00 1.60 0.50 - 0.35 max 0.60 0.05 0.18 0.30 3.10 0.30 2.10 1.70 - 0.05 0.45 inch min 0.020 - 0.005 0.007 0.114 0.006 0.075 0.059 - 0.000 0.012 nom 0.022 - 0.006 0.010 0.118 0.008 0.079 0.063 0.020 - 0.014 max 0.024 0.002 0.007 0.012 0.122 0.012 0.083 0.067 - 0.002 0.018 dimensions note: both package length and width do not include mold flash.

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